RAMBPEN=0, CMPOLPTMR0SEL=0, LPTMR3SEL=00, LPTMR2SEL=00, LPTMR1SEL=00, RAMSBDIS=0
SOPT1 Configuration Register
LPTMR1SEL | LP timer Channel1 Select 0 (00): Pad PTE4 1 (01): Pad PTF4 2 (10): Pad PTG1 |
LPTMR2SEL | LP timer Channel2 Select 0 (00): Pad PTD6 1 (01): Pad PTF3 2 (10): Pad PTG5 |
LPTMR3SEL | LP timer Channel3 Select 0 (00): Pad PTD5 1 (01): Pad PTG0 2 (10): Pad PTG6 |
CMPOLPTMR0SEL | Comparator output selection for LPTMR channel0 0 (0): CMP[1] output selected as LPTMR input[0] 1 (1): CMP[0] output selected as LPTMR input[0] |
RAMSBDIS | no description available 0 (0): Source bias of System SRAM enabled during VLPR and VLPW modes. 1 (1): Source bias of System SRAM disabled during VLPR and VLPW modes. |
RAMBPEN | RAM Bitline Precharge Enable 0 (0): Bitline precharge of system SRAM disabled during VLPR and VLPW modes. 1 (1): Bitline precharge of system SRAM enabled during VLPR and VLPW modes. |